A conventional two-port memory faces a critical VDDmin (minimum operable power supply voltage) issue when one port is in a write operation and another port is in a read operation simultaneously. In some circuits, the write operation fails when there is a timing skew on the word lines, such that there is a time overlap between a write word line (A-port) and a read word line (B-port) that is asserted after the write word line is asserted. When both word lines are asserted simultaneously, the write data is disturbed by the read word line that is precharged. The VDDmin of the memory is also limited by the simultaneous A-port write and B-port read access at the same row by two word lines.